1. Field of the Invention
The present invention relates to a semiconductor device and a liquid crystal display that comprises the semiconductor device.
2. Description of the Related Art
The structure of a conventional liquid crystal display having a thin film transistor (poly-Si TFT (Thin Film Transistor)) formed of polycrystalline silicon is shown in FIG. 14. Pixels each of which comprises a poly-Si 132 and a pixel capacitance 131 are disposed in matrix-fashion on the pixel region 124, and the gate of each poly-Si TFT 132 is connected to a gate line 134 and the drain is connected to a signal line 133. Only one pixel is shown in FIG. 14 for the purpose of simplification of the drawing herein. A gate line driving buffer 127 is disposed at the end of the gate line 134, and the gate line driving buffer 127 is scanned by means of a gate line shift register 126. The gate line shift register 126 is driven by means of a gate line clock generator 125. A signal line selection switch 123 is disposed at the end of the signal line 133, and the signal line selection switch 123 is scanned by means of a shift register 122. The signal line shift register 122 is driven by means of the signal line clock generator 121. An analog signal input line is connected to the signal line selection switch 123.
Next, the operation of FIG. 14 will be described. The gate line shift register 126 selects the gate line successively through the gate line driving buffer 127 according to the clock pulse supplied from the gate line clock generator 125. The poly-Si TFT 132 of the pixel on the selected row is set to be ON. The signal line shift register 122 scans the signal line selection switch 123 successively according to the clock pulse generated by means of the signal line clock generator 121 in the time period. The signal line selection switch 123 connects the corresponding signal line 133 to the analog signal input line 135 during scanning. Therefore, the image signal supplied to the analog signal input line 135 is written successively in the pixel capacitance 131 through the signal line 133 and the poly-Si TFT 132.
Next, the basic circuit structure of the signal line clock generator 121 is shown in FIG. 15. Each of inverters 101 to 105 and 111 to 115 comprises a CMOS circuit of poly-Si TFT. The input clock Vin is converted to the output clock xcfx86 and xcfx86(inv.) having the phase that is inverted just by angle of xcfx80 through the inverter circuits. Herein, xcfx86(inv.) means the waveform of inverted phase ideally. Because the output clock xcfx86 and xcfx86(inv.) are involved in driving of one unit signal selection switch 123 in the form of pair through the signal line sift register 122, it is important that the phase difference between both phases is equalized to xcfx80 in order to improve the image quality. For example, IDRC (International Display Research Conference) 1994 Proceedings of Technical Paper, pp. 418 to 421 describes the prior art in detail.
The above-mentioned prior art describes the method for eliminating the error of the phase difference between the output clock xcfx86 and xcfx86(inv.) of the same pair, but does not describe a method for eliminating the phase deviation between the output clock xcfx861 and xcfx862 of the different adjacent pair. If the phase deviates between both output clocks each other, when the signal selection switch 123 is turned on or turned off, the scan signal of the signal line selection switch 123 jumps from a signal selection switch 123 into the adjacent signal selection switch 123, and the jump cause a problem. In detail, when the second signal selection switch 123 that is located adjacent to the first signal selection switch 123 is turned on before the first signal selection switch 123 that is ON currently is turned off, the scan signal of the second signal selection switch 123 jumps into the first signal selection switch 123. Thereafter, when the first signal selection switch 123 is turned off, the scan signal of the first signal selection switch 123 jumps into the second signal selection switch 123. As the result, the image quality becomes poor.
The above-mentioned problem is described in detail with reference to FIG. 16 and FIG. 17. FIG. 16 shows the input/output characteristic of the inverters 103 and 113 shown in FIG. 15. xcfx861 shows the characteristic curve of the inverter 113, and xcfx862 shows the characteristic curve of the inverter 103. The logical threshold value of xcfx861 is Vth1 and that of xcfx862 is Vth2, and xcex94Vth denotes the deviation between both threshold values. The deviation is mainly due to the local dispersion of the threshold value of pMOS and nMOS that are components of the CMOS circuit, and the xcex94Vth is particularly remarkable for the CMOS circuit having poly-Si TFT. Generally, the threshold value dispersion of the single crystal Si-MOS transistor ranges approximately from 20 to 30 mV, on the other hand the threshold value dispersion of the poly-Si TFT ranges from several hundreds mV to several V. The reason why the threshold value dispersion of the poly-Si TFT is larger than that of the single crystal Si-MOS transistor in principle is that poly-Si TFT contains grain boundaries.
Next, the time t dependency of the input clock Vin on the inverter is shown in FIG. 17. The input clock Vin goes up from the low level voltage L to the high level voltage H step-wise with time. The deviation xcex94Vth between Vth1 and Vth2 corresponds to the difference xcex94t between t1 and t2 on the time axis, and xcex94t represents the logical inversion time deviation between the inverter 113 and the inverter 103. For example, it is assumed that xcex94Vth is 1 V and the inclination of the step of Vin is 107 V/s, then xcex94t of 0.1xcexc second is given. The time period of 0.1xcexc second is sufficient for the scan signal to jump from a signal selection switch 123 into the adjacent signal selection switch 123.
The dispersion of the logical threshold value of the inverter as described herein above causes the low driving voltage of the logic circuit such as poly-Si TFT circuit and is resultantly problematic in high speed operation.
It is an object of the present invention to reduce the adverse effect of the logical threshold value dispersion of the inversion logical circuit such as inverter in a semiconductor device.
The above-mentioned object is achieved by applying a method, in which in addition to the conventionally used binary logical input voltage served as the input voltage an additional DC input voltage that is set to a value between the high voltage and the low voltage of the binary logical input voltage is provided, an additional changeover means for switching between these voltages and an additional capacitance having one end connected to the output terminal of the changeover means are provided, the other end of the capacitance is connected to the input terminal of the binary inversion logical circuit, an additional switching means for holding the voltage constant while the connection between the input terminal and the output terminal of the binary inversion logical circuit is being ON is provided, and the switching means and the changeover means are set so that the switching means is turned off simultaneously at the time when or before the changeover means is switched to the binary logical input voltage.
The operation of the logical circuit is described hereinunder. When the switching means is turned on, a DC input voltage, namely the logical threshold value, is applied on the series connection of the capacitance and the binary inversion logical circuit to thereby reset the series connection. Next, while the binary logical input voltage is being applied with the switching means OFF, when the value becomes a DC input voltage, namely the logical threshold value, the binary inversion logical circuit starts the operation such as ON/OFF operation or amplification. Because such operation is triggered by the logical threshold value of the series connection that is different from the logical threshold value of the binary inversion logical circuit itself, the above object is achieved.
For example, in the case that a plurality of series connections having a capacitance and binary inversion logical circuit are connected to the changeover means in parallel, all the series connections start the operation simultaneously with one logical threshold value.
The structure of the semiconductor device and liquid crystal display having such logical circuit is described in detail hereinunder.
(1) A semiconductor device is provided with a switching means for switching between a binary logical input voltage and a DC input voltage, a capacitance having one end connected to the output terminal of the switching means, a binary inversion logical circuit having the input terminal connected to the other end of the capacitance, and a switching means for holding a constant voltage between the input terminal and output terminal of the binary inversion logical circuit in the ON state. A value of the DC input voltage is set to an intermediate value between the high voltage and the low voltage of the binary logical input voltage, and the switching means is turned off at the time when or before the switching means switches the voltage to the binary logical input voltage.
(2) In the semiconductor device as described in (1), the constant voltage of the switching means is held by short-circuiting the binary inversion logical circuit between the input terminal and the output terminal.
(3) A semiconductor device is provided with a switching means for switching between a binary logical input voltage and a DC input voltage, a plurality of first type capacitances having one ends connected to the output terminal of the switching means, a plurality of first type binary inversion logical circuits having the input terminals connected to the other ends of the plurality of first type capacitances, and a plurality of first type switching means for holding a constant voltage between the input terminals and output terminals of the plurality of first type binary inversion logical circuits in the ON state. A value of the DC input voltage is set to an intermediate value between the high voltage and the low voltage of the binary logical input voltage, and the plurality of first type switching means are turned off at the time when or before the switching means switches the voltage to the binary logical input voltage.
(4) In the semiconductor device as described in (3), the capacitance of the plurality of first type capacitances is equal to each other.
(5) In the semiconductor device as described in (3), the constant voltage of the plurality of first type switching means is held by short-circuiting the plurality of first type binary inversion logical circuits between the input terminals and the output terminals.
(6) In the semiconductor device as described in (3), the semiconductor device is additionally provided with a plurality of series-connections of second type capacitances and second type binary inversion logical circuits connected to the respective output terminals of the plurality of first type binary inversion logical circuits.
(7) In the semiconductor device as described in (6), all the plurality of series-connections have a second type switching means for holding a voltage between the respective input terminals and output terminals of the second type binary inversion logical circuit that constitute the series-connections.
(8) A liquid crystal display is provided with a pixel region on which a plurality of pixels comprising poly-Si TFT and pixel capacitances arranged in the matrix fashion and a driving means for driving the pixel region. The driving means comprises a changeover means for switching between the binary logical input voltage and the DC input voltage, a capacitance having one end connected to the output terminal of the changeover means, a binary inversion logical circuit having the input terminal connected to the other end of the capacitance, and a switching means for holding a voltage between the input terminal and the output terminal of the binary inversion logical circuit at a constant voltage in the ON state. A value of the DC input voltage is set to an intermediate value between the high voltage and the low voltage of the binary logical input voltage, and an logical circuit that turns off the switching means at the time when or before the changeover means switches the voltage to the binary logical input voltage is included.
(9) In the liquid crystal display as described in (8), the constant voltage of the switching means is held by short-circuiting the binary inversion logical circuit between the input terminal and the output terminal.
(10) In the liquid crystal display as described in (8), the ON state of the switching means and the DC input voltage state are in the vertical interval time code.
(11) In the liquid crystal display as described in (8), the ON state of the switching means and the DC input voltage state are in the horizontal interval time code.
(12) In the liquid crystal display as described in (8), the logical circuit comprises a CMOS inverter circuit having a thin film transistor.
(13) A liquid crystal display is provided with a pixel region on which a plurality of pixels comprising poly-Si TFT and pixel capacitances arranged in the matrix fashion and a driving means for driving the pixel region. The driving means comprises a change over means for switching between the binary logical input voltage and the DC input voltage, a plurality of first type capacitances having one ends connected to the output terminal of the change over means, a plurality of first type binary inversion logical circuits having the input terminals connected to the respective other ends of the plurality of first type capacitances, and a plurality of first type switching means for holding a voltage between the respective input terminals and output terminals of the plurality of first type binary inversion logical circuits at a constant voltage in the ON state. A value of the DC input voltage is set to an intermediate value between the high voltage and the low voltage of the binary logical input voltage, and a logical circuit that turns off the plurality of first type switching means at the time when or before the change over means switches the voltage to the binary logical input voltage is included.
(14) In the liquid crystal display as described in (13), the capacitance value of the plurality of first type capacitances is equal to each other.
(15) In the liquid crystal display as described in (13), the constant voltage of the plurality of first type switching means is held by short-circuiting the plurality of first type binary inversion logical circuits between the respective input terminals and output terminals.
(16) In the liquid crystal display as described in (8), the logical circuit is applied to a signal line shift register served for driving a signal line selection switch used for connecting between the signal line connected to the drain of the poly-Si TFT and the analog signal input line corresponding to the signal line, and the logical input voltage is the start pulse of the signal line shift register.
(17) In the liquid crystal display as described in (8), the logical circuit is applied to a gate line driving buffer served for driving a gate line connected to the gate of the poly-Si TFT.
(18) In the liquid crystal display as described in (13), the logical circuit is applied to a signal line clock generator.
(19) In the liquid crystal display as described in (13), the ON state of the first type switching means and the DC input voltage state of the change over means are in the vertical interval time code.
(20) In the liquid crystal display as described in (13), the ON state of the first type switching means and the DC input voltage state of the change over means are in the horizontal interval time code.
(21) In the liquid crystal display as described in (13), the logical circuit comprises a CMOS inverter circuit having a thin film transistor.
The effect of the present invention is more remarkable as the driving frequency of the circuit increases more higher. The present invention is also applicable to a single crystal Si-MOS transistor circuit.
The above and further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are purpose of illustration only and not intended as a definition of the limits of the invention.